HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 571

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

16.3.9
The STR registers are 8-bit registers that indicate status information during LPC interface
processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the
slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to
bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0. The functions for
bits 7 to 4 in STR3 differ according to the settings of bit SELSTR3 in HISEL and the TWRE bit in
LADR3L. For details, see section 16.3.13, Host Interface Select Register (HISEL). The registers
selected from the host processor according to the I/O address are described in the following
sections. For information on STR1 and STR2 selection, see section 16.3.5, LPC Channel 1,2
Address Register H, L (LADR12H, LADR12L), and information on STR3 selection, see section
16.3.4, LPC Channel 3 Address Register H, L (LADR3H, LADR3L). In an LPC I/O read cycle,
the data in the selected register is transferred to the host processor.
The STR registers are initialized to H'00 by a reset or in hardware standby mode.
• STR1
Bit
7
6
5
4
3
2
Bit Name Initial Value Slave Host Description
DBU17
DBU16
DBU15
DBU14
C/D1
DBU12
Status Registers 1 to 3 (STR1 to STR3)
All 0
0
0
R/W
R
R/W
R/W
R
R
R
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR1 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR1 contains data or a command.
0: Content of input data register (IDR1) is data
1: Content of input data register (IDR1) is a
Defined by User
The user can use this bit as necessary.
command
Rev. 3.00, 03/04, page 529 of 830