HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 583
HD64F2168VTE33
Manufacturer Part Number
HD64F2168VTE33
Description
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F2168VTE33.pdf
(876 pages)
Specifications of HD64F2168VTE33
Cpu Family
H8S
Device Core Size
16/32Bit
Frequency (max)
33MHz
Interface Type
I2C/IrDA/SCI
Program Memory Type
Flash
Program Memory Size
256KB
Total Internal Ram Size
40KB
# I/os (max)
106
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2168VTE33V
Manufacturer:
Renesas
Quantity:
8 400
Company:
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS
Quantity:
112
Part Number:
HD64F2168VTE33V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bit
5
4
IRQ9E3
IRQ6E3
Bit Name Initial Value Slave Host Description
0
0
R/W
R/W
R/W
Host IRQ9 Interrupt Enable 3
Enables or disables a HIRQ9 interrupt request when
OBF3A is set by an ODR3 write.
0: HIRQ9 interrupt request by OBF3A and IRQ9E3
[Clearing conditions]
•
•
•
1: [When IEDIR3 = 0]
[Setting condition]
•
Host IRQ6 Interrupt Enable 3
Enables or disables a HIRQ6 interrupt request when
OBF3A is set by an ODR3 write.
0: HIRQ6 interrupt request by OBF3A and IRQ6E3
[Clearing conditions]
•
•
•
1: [When IEDIR3 = 0]
[Setting condition]
•
[When IEDIR3 = 1]
[When IEDIR3 = 1]
is disabled
HIRQ9 interrupt request by setting OBF3A to 1 is
enabled
HIRQ9 interrupt is requested.
is disabled
HIRQ6 interrupt request by setting OBF3A to 1 is
enabled
HIRQ6 interrupt is requested.
Writing 0 to IRQ9E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR3 = 0)
Writing 1 after reading IRQ9E3 = 0
Writing 0 to IRQ6E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR3 = 0)
Writing 1 after reading IRQ6E3 = 0
Rev. 3.00, 03/04, page 541 of 830
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