HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 238

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

8.4
Port 4 is an 8-bit I/O port. Port 4 pins also function as external interrupt input, and TMR_0,
TMR_1, TMR_X, and TMR_Y input/output pins. Port 4 has the following registers.
• Port 4 data direction register (P4DDR)
• Port 4 data register (P4DR)
8.4.1
The individual bits of P4DDR specify input or output for the pins of port 4.
8.4.2
P4DR stores output data for the port 4 pins.
Rev. 3.00, 03/04, page 196 of 830
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
P47DDR
P46DDR
P45DDR
P44DDR
P43DDR
P42DDR
P41DDR
P40DDR
Bit Name
P47DR
P46DR
P45DR
P44DR
P43DR
P42DR
P41DR
P40DR
Port 4
Port 4 Data Direction Register (P4DDR)
Port 4 Data Register (P4DR)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W Description
W
W
W
W
W
W
W
W
R/W Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If port 4 pins are specified for use as the general I/O
port, the corresponding port 4 pins are output ports
when the P4DDR bits are set to 1, and input ports when
cleared to 0.
P4DR stores output data for the port 4 pins that are
used as the general output port.
If a port 4 read is performed while the P4DDR bits are
set to 1, the P4DR values are read. If a port 4 read is
performed while the P4DDR bits are cleared to 0, the
pin states are read.