mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 1000

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.12 Port K Data Direction Register (DDRK)
Read: Anytime.
Write: Anytime.
This register controls the data direction for port K. DDRK determines whether each pin (except PK6) is
an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0”
causes the associated pin to be a high-impedance input.
24.0.5.13 Port T Data Register (PTT)
Read: Anytime.
Write: Anytime.
1000
DDRK[7,5:0]
PK[7,5:0]
Reset
Reset
Field
Field
ECT
7–0
7–0
W
W
R
R
DDRK7
PTT7
IOC7
Port K — Port K pins 7–0 can be used as general-purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read
except for bit 6 which reads “0”.
Data Direction Port K
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
0
7
7
on PORTK after changing the DDRK register.
PTT6
IOC6
0
0
0
6
6
Figure 24-14. Port K Data Direction Register (DDRK)
Figure 24-15. Port T Data Register (PTT)
Table 24-15. PORTK Field Descriptions
Table 24-16. DDRK Field Descriptions
DDRK5
MC9S12XDP512 Data Sheet, Rev. 2.17
PTT5
IOC5
0
0
5
5
DDRK4
PTT4
IOC4
0
0
4
4
Description
Description
DDRK3
PTT3
IOC3
0
0
3
3
DDRK2
PTT2
IOC2
0
0
2
2
DDRK1
Freescale Semiconductor
PTT1
IOC1
0
0
1
1
DDRK0
PTT0
IOC0
0
0
0
0