mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 227

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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BFEXT
Operation
RS1[(o+w):o]
Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD.
The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
BFEXT RD, RS1, RS2
N
0
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
w = (RS2[7:4])
o = (RS2[3:0])
V
0
Source Form
C
RD[w:0]; 0
15
15
15
RD[15:(w+1)]
Address
MC9S12XDP512 Data Sheet, Rev. 2.17
Mode
TRI
0
Bit Field Extract
0
7
1
1
W4
0
5
W4=3, O4=2
0
4
3
3
Machine Code
RD
2
O4
Bit Field Extract
RS1
0
0
0
RS2
RS1
RD
Chapter 6 XGATE (S12XGATEV2)
BFEXT
RS2
1
1
Cycles
P
227

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