mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 939

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

DDRM[7:0]
Reset
Reset
23.0.5.31 Port M Input Register (PTIM)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to
detect overload or short circuit conditions on output pins.
23.0.5.32 Port M Data Direction Register (DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN). also forces the I/O state to be an input for each port line associated with an enabled
input (RXCAN). In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Field
7–0
W
associated pin values.
W
R
R
1
DDRM7
PTIM7
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
—
7
7
0
on PTM or PTIM registers, when changing the DDRM register.
= Unimplemented or Reserved
DDRM6
PTIM6
—
0
6
6
Figure 23-34. Port M Data Direction Register (DDRM)
Figure 23-33. Port M Input Register (PTIM)
Table 23-33. DDRM Field Descriptions
DDRM5
PTIM5
—
5
5
0
DDRM4
PTIM4
—
0
4
4
Description
DDRM3
PTIM3
—
3
3
0
DDRM2
PTIM2
—
0
2
2
DDRM1
PTIM1
—
1
1
0
DDRM0
PTIM0
—
0
0
0