mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 400

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
The equation used to generate the divider values from the IBFD bits is:
400
SCL
SDA
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
SDA
SCL
START condition
Table
Table
9-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
9-3, all subsequent tap points are separated by 2
Figure 9-5. SCL Divider and SDA Hold
MC9S12XDP512 Data Sheet, Rev. 2.17
SCL Hold(start)
Table 9-4. Multiplier Factor
IBC7-6
00
01
10
11
SCL Divider
RESERVED
MUL
01
02
04
STOP condition
SDA Hold
IBC5-3
Table
Freescale Semiconductor
as shown in the
SCL Hold(stop)
9-4.