mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 215

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

6.8.3
Table 6-16
implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are
not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible
every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit
operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.
6.8.4
When the RISC core is triggered by an interrupt request (see
sequence which performs three bus accesses:
Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If
further interrupt requests are pending after a thread has been terminated, a new vector fetch will be
performed. Otherwise the RISC core will idle until a new interrupt request is received. A thread can not be
interrupted by an interrupt request.
6.8.5
This section describes the XGATE instruction set in alphabetical order.
Freescale Semiconductor
1. A V-cycle to fetch the initial content of the program counter.
2. A V-cycle to fetch the initial content of the data segment pointer (R1).
3. A P-cycle to load the initial opcode.
V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
r — 8 bit data read: lasts for at least one RISC core cycle
R — 16 bit data read: lasts for at least one RISC core cycle
w — 8 bit data write: lasts for at least one RISC core cycle
W — 16 bit data write: lasts for at least one RISC core cycle
A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
f — Free cycle: no read or write, lasts for one RISC core cycles
Special Cases
PP/P — Branch: PP if branch taken, P if not
show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter
Cycle Notation
Thread Execution
Instruction Glossary
Table 6-16. Access Detail Notation
MC9S12XDP512 Data Sheet, Rev. 2.17
Figure
6-1) it first executes a vector fetch
Chapter 6 XGATE (S12XGATEV2)
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