mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 645

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses is the following:
Freescale Semiconductor
An aligned word access to a PRR will take 2 bus cycles.
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
PRR Name
MMCCTL0
MMCCTL1
ECLKCTL
Reserved
Reserved
EBICTL0
EBICTL1
PORTC
PORTD
PORTB
PORTE
PORTK
PORTA
RDRIV
MODE
DDRA
DDRB
DDRC
DDRD
DDRE
PUCR
DDRK
MC9S12XDP512 Data Sheet, Rev. 2.17
Table 17-23. PRR Listing
PRR Local Address
$000C
$000D
$001C
$001D
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000E
$000F
$0012
$0013
$0032
$0033
Chapter 17 Memory Mapping Control (S12XMMCV2)
PRR Location
MMC
MMC
MMC
MMC
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
EBI
EBI
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