mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 1002

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
24.0.5.16 Port T Reduced Drive Register (RDRT)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
24.0.5.17 Port T Pull Device Enable Register (PERT)
Read: Anytime.
Write: Anytime.
1002
DDRT[7:0]
RDRT[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
RDRT7
PERT7
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port T
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
0
0
7
7
on PTT or PTIT registers, when changing the DDRT register.
RDRT6
PERT6
Figure 24-19. Port T Pull Device Enable Register (PERT)
0
0
6
6
Figure 24-18. Port T Reduced Drive Register (RDRT)
Table 24-19. DDRT Field Descriptions
Table 24-20. RDRT Field Descriptions
RDRT5
PERT5
MC9S12XDP512 Data Sheet, Rev. 2.17
0
0
5
5
RDRT4
PERT4
0
0
4
4
Description
Description
RDRT3
PERT3
0
0
3
3
RDRT2
PERT2
0
0
2
2
RDRT1
PERT1
Freescale Semiconductor
0
0
1
1
RDRT0
PERT0
0
0
0
0