mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 104

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.4.2.2
The VCO has a minimum operating frequency, f
to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO
running at minimum operating frequency; this mode of operation is called self clock mode. This requires
CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self clock mode, the
PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically
select OSCCLK to be the system clock and return to normal mode.
Checker”
2.4.3
This section summarizes the low power options available in the CRG.
2.4.3.1
The RTI can be stopped by setting the associated rate select bits to 0.
The COP can be stopped by setting the associated rate select bits to 0.
2.4.3.2
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during wait mode.
Table 2-11
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG
then checks whether the PLLWAI bit is asserted
switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the PLL. As
soon as all clocks are switched off wait mode is active.
104
.
for more information on entering and leaving self clock mode.
lists the individual configuration bits and the parts of the MCU that are affected in wait mode
Low Power Options
Self Clock Mode
Run Mode
Wait Mode
In order to detect a potential clock loss the CME bit should be always
enabled (CME = 1)!
If CME bit is disabled and the MCU is configured to run on PLL clock
(PLLCLK), a loss of external clock (OSCCLK) will not be detected and will
cause the system clock to drift towards the VCO’s minimum frequency
f
ramps up to its PLL target frequency. If the MCU is running on external
clock any loss of clock will cause the system to go static.
SCM
. As soon as the external clock is available again the system clock
Table 2-11. MCU Configuration During Wait Mode
COP
PLL
RTI
MC9S12XDP512 Data Sheet, Rev. 2.17
PLLWAI
Stopped
—
—
(Figure
SCM
NOTE
. If the external clock frequency is not available due
Stopped
RTIWAI
—
—
2-21). Depending on the configuration, the CRG
COPWAI
Section 2.4.1.4, “Clock Quality
Stopped
—
—
Freescale Semiconductor