mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 959

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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DDR0AD1[23:16]
Reset
Reset
23.0.5.67 Port AD1 Data Register 1 (PT1AD1)
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[15:8]. These pins can also be used as general
purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
23.0.5.68 Port AD1 Data Direction Register 0 (DDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures pin PAD[23:16] as either input or output.
Field
W
W
R
R
7–0
DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116
PT1AD115
7
0
7
0
Data Direction Port AD1 Register 0
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has
PT1AD114
read on PTAD10 register, when changing the DDR0AD1 register.
to be set to logic level “1”.
Figure 23-70. Port AD1 Data Direction Register 0 (DDR0AD1)
0
0
6
6
Figure 23-69. Port AD1 Data Register 1 (PT1AD1)
Table 23-61. DDR0AD1 Field Descriptions
PT1AD113
5
0
5
0
PT1AD112
0
0
4
4
Description
PT1AD111
3
0
3
0
PT1AD110
0
0
2
2
PT1AD19
1
0
1
0
PT1AD18
0
0
0
0

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