mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 609

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the
CPU will default to that of the spurious interrupt vector.
16.4.5
The XINT supports three system reset exception request types (please refer to CRG for details):
16.4.6
The priority (from highest to lowest) and address of all exception vectors issued by the XINT upon request
by the CPU is shown in
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Freescale Semiconductor
(Vector base + 0x00F0–0x0012) Device specific I bit maskable interrupt sources (priority determined by the associated
16 bits vector address based
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0010)
Vector Address
0xFFFE
0xFFFC
0xFFFA
Reset Exception Requests
Exception Priority
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
1
Table
Pin reset, power-on reset, low-voltage reset, illegal address reset
Clock monitor reset
COP watchdog reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
XIRQ interrupt request
IRQ interrupt request
configuration registers, in descending order)
Spurious interrupt
Table 16-8. Exception Vector Map and Priority
16-8.
MC9S12XDP512 Data Sheet, Rev. 2.17
NOTE
Source
Chapter 16 Interrupt (S12XINTV1)
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