mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 526
mc9s12xd256
Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12XD256.pdf
(1350 pages)
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Chapter 12 Serial Peripheral Interface (S12SPIV4)
12.3.2.5
Read: Anytime; normally read only when SPIF is set
Write: Anytime
526
Reset
W
R
The SPI data register is both the input and output register for SPI data. A write to this register
allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data
byte is transmitted immediately after the previous transmission has completed. The SPI transmitter
empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new
data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and a byte has been received, the received byte is transferred from the receive
shift register to the SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second byte has been received, the second received byte is
kept as valid byte in the receive shift register until the start of another transmission. The byte in the
SPIDR does not change.
If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of
a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF
remains set (see
If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of
a third transmission, the byte in the receive shift register has become invalid and is not transferred
into the SPIDR (see
Bit 7
SPI Data Register (SPIDR)
0
7
Figure
6
0
6
Figure
12-8).
Figure 12-7. SPI Data Register (SPIDR)
12-9).
MC9S12XDP512 Data Sheet, Rev. 2.17
5
0
5
4
0
4
3
0
3
2
0
2
Freescale Semiconductor
2
0
1
Bit 0
0
0
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