mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 94

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.2.9
This register controls the COP (computer operating properly) watchdog.
Read: Anytime
Write:
The COP time-out period is restarted if one these two conditions is true:
94
1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0.
Reset
RSBCK
WCOP
1. RSBCK: Anytime in special modes; write to “1” but not to “0” in all other modes
2. WCOP, CR2, CR1, CR0:
1. Writing a nonzero value to CR[2:0] (anytime in special modes, once in all other modes) with
2. Changing RSBCK bit from “0” to “1”.
Field
7
6
W
R
1
— Anytime in special modes
— Write once in all other modes
WRTMASK = 0.
Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, 0x_55 can be written as often as desired. Once 0x_AA is written after the 0x_55, the time-out logic
restarts and the user must wait until the next window before writing to ARMCOP.
of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in active BDM mode.
1 Stops the COP and RTI counters whenever the part is in active BDM mode.
CRG COP Control Register (COPCTL)
7
or
= Unimplemented or Reserved
RSBCK
0
6
Figure 2-12. CRG COP Control Register (COPCTL)
WRTMASK
Table 2-9. COPCTL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.17
0
0
5
0
0
4
Description
0
0
3
CR2
2
Table 2-10
Freescale Semiconductor
CR1
1
shows the duration
CR0
0