mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 652

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.1.1
18.1.2
The main features of this block are:
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Unimplemented areas
Mis-aligned address
single-chip modes
Paging capability to support a global 8 Mbytes memory address space
Bus arbitration between the masters CPU, BDM and XGATE
external resource
expanded modes
emulation modes
Aligned address
External Space
global address
normal modes
special modes
Logic level “1”
Logic level “0”
local address
Bus Clock
Terminology
Features
MCU
NVM
word
PRR
PRU
byte
NS
SS
NX
ES
EX
ST
0x
x
Voltage that corresponds to Boolean true state
Voltage that corresponds to Boolean false state
Represents hexadecimal number
Represents logic level ’don’t care’
8-bit data
16-bit data
based on the 64 KBytes Memory Space (16-bit address)
based on the 8 MBytes Memory Space (23-bit address)
Address on even boundary
Address on odd boundary
System Clock. Refer to CRG Block Guide.
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
Normal Single-Chip Mode
Special Single-Chip Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Normal Single-Chip Mode
Normal Expanded Mode
Special Single-Chip Mode
Special Test Mode
Normal Single-Chip Mode
Special Single-Chip Mode
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
Area which is accessible in the global address range 14_0000 to 3F_FFFF
Resources (Emulator, Application) connected to the MCU via the external bus on
expanded modes (Unimplemented areas and External Space)
Port Replacement Registers
Port Replacement Unit located on the emulator side
MicroController Unit
Non-volatile Memory; Flash EEPROM or ROM
Table 18-1. Acronyms and Abbreviations
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor