mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 322

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.6
Read or write: Anytime except PRNT bit is write once
All bits reset to zero.
322
TSFRZ
TFFCA
TSWAI
Reset
PRNT
Field
TEN
7
6
5
4
3
W
R
TEN
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
Note: If for any reason the timer is not active, there is no 64 clock for the pulse accumulator since the 64 is
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode.
Timer and Modulus Counter Stop While in Freeze Mode
0 Allows the timer and modulus counter to continue running while in freeze mode.
1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation.
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 A read from an input capture or a write to the output compare channel registers causes the corresponding
Note: The flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag) when
Precision Timer
0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the
1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR
Timer System Control Register 1 (TSCR1)
0
7
Timer interrupts cannot be used to get the MCU out of wait.
The pulse accumulators do not stop in freeze mode.
channel flag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF flag
in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.
Any access to the MCCNT register clears the MCZF flag in the MCFLG register. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag
clearing due to unintended accesses.
delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection.
MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection.
register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the
prescaler Precision Timer Modulus Counter Prescaler selection.
generated by the timer prescaler.
TFFCA = 1.
= Unimplemented or Reserved
TSWAI
0
6
Figure 7-9. Timer System Control Register 1 (TSCR1)
Table 7-7. TSCR1 Field Descriptions
TSFRZ
MC9S12XDP512 Data Sheet, Rev. 2.17
0
5
TFFCA
0
4
Description
PRNT
0
3
0
0
2
Freescale Semiconductor
0
0
1
0
0
0