mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 1004

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status
bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be
used as general purpose I/O.
Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and
1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and
0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with
the SCI, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
24.0.5.20 Port S Input Register (PTIS)
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This also can be used to detect
overload or short circuit conditions on output pins.
24.0.5.21 Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
1004
Reset
Reset
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
W
associated pin values.
W
R
R
1
DDRS7
PTIS7
—
0
7
7
= Unimplemented or Reserved
DDRS6
PTIS6
—
0
6
6
Figure 24-23. Port S Data Direction Register (DDRS)
Figure 24-22. Port S Input Register (PTIS)
DDRS5
MC9S12XDP512 Data Sheet, Rev. 2.17
PTIS5
—
0
5
5
DDRS4
PTIS4
—
0
4
4
DDRS3
PTIS3
—
0
3
3
DDRS2
PTIS2
—
0
2
2
DDRS1
Freescale Semiconductor
PTIS1
—
0
1
1
DDRS0
PTIS0
—
0
0
0