mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 107

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
CME
0
1
1
1
SCME
X
0
1
1
SCMIE
X
X
0
1
Clock failure -->
Clock failure -->
Clock failure -->
Clock failure -->
SCMIF generates self clock mode wakeup interrupt.
Table 2-12. Outcome of Clock Loss in Wait Mode
Scenario 1: OSCCLK recovers prior to exiting wait mode.
Scenario 2: OSCCLK does not recover prior to exiting wait mode.
No action, clock loss not detected.
CRG performs Clock Monitor Reset immediately
Some time later OSCCLK recovers.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External Reset is applied.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External RESET is applied.
– MCU remains in wait mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,
– SCM deactivated,
– PLL disabled depending on PLLWAI,
– VREG remains enabled (never gets disabled in wait mode).
– MCU remains in wait mode.
– Exit wait mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
– Exit wait mode using OSCCLK as system clock,
– Start reset sequence.
– MCU remains in wait mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag,
– Keep performing clock quality checks (could continue infinitely) while in wait mode.
– Exit wait mode in SCM using PLL clock (f
– Continue to perform additional clock quality checks until OSCCLK is o.k. again.
– Exit wait mode in SCM using PLL clock (f
– Start reset sequence,
– Continue to perform additional clock quality checks until OSCCLKis o.k.again.
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– SCMIF set.
– Exit wait mode in SCM using PLL clock (f
– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.
MC9S12XDP512 Data Sheet, Rev. 2.17
CRG Actions
Chapter 2 Clocks and Reset Generator (S12CRGV6)
SCM
SCM
SCM
) as system clock,
) as system clock,
) as system clock,
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