mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 686

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 18 Memory Mapping Control (S12XMMCV3)
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
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An aligned word access to a PRR will take 2 bus cycles.
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
PRR Name
MMCCTL0
MMCCTL1
ECLKCTL
Reserved
Reserved
EBICTL0
EBICTL1
PORTC
PORTD
PORTB
PORTE
PORTK
PORTA
RDRIV
MODE
DDRA
DDRB
DDRC
DDRD
DDRE
PUCR
DDRK
MC9S12XDP512 Data Sheet, Rev. 2.17
Table 18-24. PRR Listing
PRR Local Address
0x000C
0x000D
0x001C
0x001D
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000E
0x000F
0x0012
0x0013
0x0032
0x0033
PRR Location
MMC
MMC
MMC
MMC
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
EBI
EBI
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