mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 205

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Figure 6-22
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
6.4.5
The XGATE module will immediately terminate program execution after detecting an error condition
caused by erratic application code. There are three error conditions:
All opcodes which are not listed in section
and opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
Freescale Semiconductor
Execution of an illegal opcode
Illegal vector or opcode fetches
Illegal load or store accesses
Software Error Detection
gives an example of the typical usage of the XGATE hardware semaphores.
Figure 6-22. Algorithm for Locking and Releasing Semaphores
XGSEM
S12X_CPU
%1
XGSEM
sequence
critical
.........
.........
code
XGSEMx
MC9S12XDP512 Data Sheet, Rev. 2.17
%1?
%0
Section 6.8, “Instruction Set”
XGATE
sequence
critical
CSEM
SSEM
.........
BCC?
.........
code
are illegal opcodes. Illegal vector
Chapter 6 XGATE (S12XGATEV2)
205

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