mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 567

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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14.4.10.1 Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage V
status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V
interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable
bit LVIE = 1.
14.4.10.2 Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated
by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
Freescale Semiconductor
On entering the reduced power mode, the LVIF is not cleared by the
VREG_3V3.
Autonomous periodical interrupt (API)
Interrupt Source
MC9S12XDP512 Data Sheet, Rev. 2.17
Table 14-10. Interrupt Vectors
NOTE
DDA
. Whenever V
Local Enable
APIE = 1
Chapter 14 Voltage Regulator (S12VREG3V3V5)
DDA
DDA
drops below level V
rises above level V
LVIA,
LVID
the
. An
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