mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 328

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.12
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA
bit in
Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers, instead of
generating an interrupt for every capture.
328
C[7:0]F
Reset
Field
7:0
Section 7.3.2.6, “Timer System Control Register 1
W
R
Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or
output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be
set by 8-bit pulse accumulators PAC3–PAC0.
If the delay counter is enabled, the CxF flag will not be set until after the delay.
C7F
Main Timer Interrupt Flag 1 (TFLG1)
0
7
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
C6F
0
6
Figure 7-17. Main Timer Interrupt Flag 1 (TFLG1)
Table 7-16. TFLG1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.17
C5F
0
5
(TSCR1)”.
C4F
NOTE
0
4
Description
(TSCR1)”).
C3F
0
3
Section 7.3.2.6, “Timer
C2F
0
2
Freescale Semiconductor
C1F
0
1
C0F
0
0