mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 469

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

If sleep mode is active, the SLPRQ and SLPAK bits are set
use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode.
When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks
that allow register accesses from the CPU side continue to run.
If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits
due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be
read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO
(RxFG) does not take place while in sleep mode.
It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes
place while in sleep mode.
If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. The
RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode
(Figure
The MSCAN is able to leave sleep mode (wake up) only when:
Freescale Semiconductor
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If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will
continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted
successfully or aborted) and then goes into sleep mode.
If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN
bus next becomes idle.
If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.
CAN bus activity occurs and WUPE = 1
10-46). WUPE must be set before entering sleep mode to take effect.
The application software must avoid setting up a transmission (by clearing
one or more TXEx flag(s)) and immediately request sleep mode (by setting
SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode
directly depends on the exact sequence of operations.
Bus Clock Domain
CPU
Sleep Request
SLPAK
Flag
Figure 10-45. Sleep Request / Acknowledge Cycle
SLPRQ
sync.
SLPAK
MC9S12XDP512 Data Sheet, Rev. 2.17
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
NOTE
SYNC
SYNC
CAN Clock Domain
(Figure
sync.
SLPRQ
SLPAK
10-45). The application software must
MSCAN
in Sleep Mode
SLPRQ
Flag
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