mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 256

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 6 XGATE (S12XGATEV2)
CSR
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
256
N:
Z:
V:
C:
CSR RD, #IMM4
CSR RD, RS
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Z
V
Source Form
old
^ RD[15]
C
new
C
C
n bits
C
Logical Shift Right with Carry
Address
MC9S12XDP512 Data Sheet, Rev. 2.17
Mode
IMM4
C
DYA
0
0
0
0
0
0
0
0
RD
n
1
1
Machine Code
RD
RD
RS
IMM4
C
1
1
0
Freescale Semiconductor
0
0
CSR
1
1
1
1
Cycles
P
P

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