mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 390

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
As an example of a center aligned output, consider the following case:
Shown in
8.4.2.7
The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater
PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.
The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and
5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and
channels 0 and 1 are concatenated with the CON01 bit.
When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double
byte channel, as shown in
registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated,
channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are
concatenated, channel 0 registers become the high order bytes of the double byte channel.
When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel
clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when
channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when
channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order
8-bit channel as also shown in
PPOLx bit of the corresponding low order 8-bit channel as well.
390
E = 100 ns
Clock Source = E, where E = 10 MHz (100 ns period)
PWMx Frequency = 10 MHz/8 = 1.25 MHz
PWMx Period = 800 ns
PWMx Duty Cycle = 3/4 *100% = 75%
Figure 8-23
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWM 16-Bit Functions
Change these bits only when both corresponding channels are disabled.
Figure 8-23. PWM Center Aligned Output Example Waveform
is the output waveform generated.
Figure
Figure
8-24. Similarly, when channels 4 and 5 are concatenated, channel 4
MC9S12XDP512 Data Sheet, Rev. 2.17
8-24. The polarity of the resulting PWM output is controlled by the
DUTY CYCLE = 75%
PERIOD = 800 ns
NOTE
Freescale Semiconductor
E = 100 ns