mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 684

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.4.4.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
18.4.5
18.4.5.1
The following interrupt requests can be triggered by the MMC module:
CPU access violation: The CPU access violation signals to the CPU detection of an error condition in the
CPU application code which is resulted in write access to the protected XGATE RAM area (see
Section 18.4.3.2, “Illegal CPU
18.5
18.5.1
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
called can be located anywhere in the local address space or in any Flash or ROM page visible through the
program page window. The CALL instruction calculates and stacks a return address, stacks the current
PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value
controls which of the 256 possible pages is visible through the 16 Kbyte program page window in the
64 Kbyte local CPU memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
684
•
•
•
•
•
1. Writes the current PPAGE value into an internal temporary register and writes the new
2. Calculates the address of the next instruction after the CALL instruction (the return address) and
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new
CPU always has priority over BDM and XGATE.
XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
XGATE has priority over BDM.
BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the
later case the suspect master will be stalled after finishing the current operation and the BDM will
gain access to the bus.
In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
instruction-supplied PPAGE value into the PPAGE register
pushes this 16-bit value onto the stack
address
Initialization/Application Information
Interrupts
CALL and RTC Instructions
Master Bus Prioritization regarding Access Conflicts on Target Buses
Outgoing Interrupt Requests
Accesses).
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor