mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 431

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are
read-only; write of 1 clears flag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
Freescale Semiconductor
RSTAT[1:0]
TSTAT[1:0]
WUPIF
CSCIF
Field
5:4
3:2
7
6
Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see
“MSCAN Sleep
(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
0
1
CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status
due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional
4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the
system on the actual CAN bus status (see
(CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking
interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no
CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is
asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status
until the current CSCIF interrupt is cleared again.
0
1
Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00
01
10
11
Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.
As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00
01
10
11
The CANRFLG register is held in the reset state
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
No wake-up activity observed while in sleep mode
MSCAN detected activity on the CAN bus and requested wake-up
No change in CAN bus status occurred since last interrupt
MSCAN changed current CAN bus status
RxOK: 0
RxWRN: 96
RxERR: 127
Bus-off
TxOK: 0
TxWRN: 96
TxERR: 127
Bus-Off: transmit error counter
1
: transmit error counter
Mode,”) and WUPE = 1 in CANTCTL0 (see
transmit error counter
receive error counter
Table 10-9. CANRFLG Register Field Descriptions
transmit error counter
transmit error counter
receive error counter
receive error counter
MC9S12XDP512 Data Sheet, Rev. 2.17
255
255
96
96
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register
NOTE
127
127
255
Description
Section 10.3.2.1, “MSCAN Control Register 0
1
when the initialization
Section 10.4.5.4,
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