mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 516

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 12 Serial Peripheral Interface (S12SPIV4)
This is a high level description only, detailed descriptions of operating modes are contained in
Section 12.4.7, “Low Power Mode
12.1.4
Figure 12-1
data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock
generation turned off. If the SPI is configured as a master, any transmission in progress stops, but
is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of a byte continues, so that the slave stays
synchronized to the master.
Block Diagram
gives an overview on the SPI architecture. The main parts of the SPI are status, control and
Options”.
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor