mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 763

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

20.3.2.8.1
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Read: Anytime
Write: Anytime when S12XDBG not armed.
Freescale Semiconductor
Address: 0x0028
Address: 0x0028
(Comparators
(Comparators
(Comparators
Reset
Reset
B and D)
A and C
B nd D)
Field
NDB
SZE
TAG
W
W
SZ
R
R
7
6
6
5
SZE
0
0
0
7
7
Debug Comparator Control Register (DBGXCTL)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
Not Data Bus Compare — The NDB bit controls whether the match occurs when the data bus matches the
comparator register value or when the data bus differs from the register value. Furthermore data bus bits can
be individually masked using the comparator data mask registers. This bit is only available for comparators
A and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality
for comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
Figure 20-13. Debug Comparator Control Register (Comparators A and C)
Figure 20-14. Debug Comparator Control Register (Comparators B and D)
= Unimplemented or Reserved
NDB
SZ
0
0
6
6
Table 20-27. DBGXCTL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.17
TAG
TAG
0
0
5
5
BRK
BRK
0
0
4
4
Description
RW
RW
0
0
3
3
Chapter 20 S12X Debug (S12XDBGV3) Module
RWE
RWE
0
0
2
2
SRC
SRC
0
0
1
1
COMPE
COMPE
0
0
0
0
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