mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 857

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

22.3.2.40 Port P Data Direction Register (DDRP)
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0
channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for
details.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.
Freescale Semiconductor
DDRP[7:0]
Reset
Field
7–0
W
R
DDRP7
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTP or PTIP registers, when changing the DDRP register.
DDRP6
0
6
Figure 22-42. Port P Data Direction Register (DDRP)
Table 22-39. DDRP Field Descriptions
DDRP5
MC9S12XDP512 Data Sheet, Rev. 2.17
0
5
DDRP4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRP3
0
3
DDRP2
0
2
DDRP1
0
1
DDRP0
0
0
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