mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 934

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.23 Port S Data Register (PTS)
Read: Anytime.
Write: Anytime.
Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status
bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be
used as general purpose I/O.
Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and
1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and
0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with
the SCI, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
23.0.5.24 Port S Input Register (PTIS)
934
SCI/SPI
PPST[7:0]
Reset
Reset
Field
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
7–0
W
W
associated pin values.
R
R
1
PTIS7
PTS7
Pull Select Port T
0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT
1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT
SS0
—
0
7
7
and if the port is used as input.
and if the port is used as input.
= Unimplemented or Reserved
PTIS6
SCK0
PTS6
—
0
6
6
Figure 23-26. Port S Input Register (PTIS)
Figure 23-25. Port S Data Register (PTS)
Table 23-26. PPST Field Descriptions
MOSI0
MC9S12XDP512 Data Sheet, Rev. 2.17
PTIS5
PTS5
—
0
5
5
MISO0
PTIS4
PTS4
—
0
4
4
Description
PTIS3
TXD1
PTS3
—
0
3
3
PTIS2
RXD1
PTS2
—
0
2
2
Freescale Semiconductor
PTIS1
TXD0
PTS1
—
0
1
1
PTIS0
RXD0
PTS0
—
0
0
0