mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 994

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.4
Read: Anytime.
Write: Anytime.
24.0.5.5
Read: Anytime.
Write: Anytime.
994
DDRB[7:0]
Reset
Reset
Func.
Field
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
7–0
Alt.
W
W
associated pin values.
R
R
ECLKX2
DDRB7
XCLKS
Data Direction Port B — This register controls the data direction for port B. DDRB determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
PE7
Port B Data Direction Register (DDRB)
Port E Data Register (PORTE)
or
0
0
7
7
on PORTB after changing the DDRB register.
= Unimplemented or Reserved
DDRB6
MODB
PE6
0
0
6
6
Figure 24-6. Port B Data Direction Register (DDRB)
Figure 24-7. Port E Data Register (PORTE)
Table 24-7. DDRB Field Descriptions
DDRB5
MC9S12XDP512 Data Sheet, Rev. 2.17
MODA
PE5
0
0
5
5
DDRB4
ECLK
PE4
0
0
4
4
Description
EROMCTL
DDRB3
PE3
0
0
3
3
DDRB2
PE2
0
0
2
2
DDRB1
Freescale Semiconductor
PE1
IRQ
—
0
1
1
1
DDRB0
XIRQ
PE0
—
0
0
0
1