mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 1005

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

DDRS[7:0]
RDRS[7:0]
Reset
Reset
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
Field
24.0.5.22 Port S Reduced Drive Register (RDRS)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port S output pin as either full or reduced. If the
port is used as input this bit is ignored.
Field
24.0.5.23 Port S Pull Device Enable Register (PERS)
Read: Anytime.
7–0
7–0
W
W
R
R
RDRS7
PERS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port S
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
7
0
7
1
on PTS or PTIS registers, when changing the DDRS register.
RDRS6
PERS6
Figure 24-25. Port S Pull Device Enable Register (PERS)
0
1
6
6
Figure 24-24. Port S Reduced Drive Register (RDRS)
Table 24-23. DDRS Field Descriptions
Table 24-24. RDRS Field Descriptions
RDRS5
PERS5
5
0
5
1
RDRS4
PERS4
0
1
4
4
Description
Description
RDRS3
PERS3
3
0
3
1
RDRS2
PERS2
0
1
2
2
RDRS1
PERS1
1
0
1
1
RDRS0
PERS0
0
1
0
0