mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 529

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.4.1
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate
transmissions. A transmission begins by writing to the master SPI data register. If the shift register is
empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin
under the control of the serial clock.
Freescale Semiconductor
•
•
•
Serial clock
The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and
SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and
determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK
pin, the baud rate generator of the master controls the shift register of the slave peripheral.
MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin
(MISO) is determined by the SPC0 and BIDIROE control bits.
SS pin
If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output
becomes low during each transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault
error. If the SS input becomes low this indicates a mode fault error where another master tries to
drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by
clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional
mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a
transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is
forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If
the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt
sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After
the delay, SCK is started within the master. The rest of the transfer operation differs slightly,
depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1
(see
Master Mode
Section 12.4.3, “Transmission
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or
BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode
will abort a transmission in progress and force the SPI into idle state. The
remote slave cannot detect this, therefore the master must ensure that the
remote slave is returned to idle state.
MC9S12XDP512 Data Sheet, Rev. 2.17
Formats”).
NOTE
Chapter 12 Serial Peripheral Interface (S12SPIV4)
529