mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 196

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6 XGATE (S12XGATEV2)
6.3.1.6
The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and
the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by
the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM
instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register
(Figure
Read: Anytime
Write: Anytime (see
196
Reset
XGSEMM[7:0]
XGSEM[7:0]
W
R
Field
15–8
7–0
6-8). Refer to section
15
0
0
XGATE Semaphore Register (XGSEM)
Semaphore Mask — These bits control the write access to the XGSEM bits.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
14
0
0
13
0
0
Section 6.4.4,
XGSEMM[7:0]
12
0
0
Figure 6-8. XGATE Semaphore Register (XGSEM)
Section 6.4.4, “Semaphores”
11
0
0
Table 6-6. XGSEM Field Descriptions
“Semaphores”)
MC9S12XDP512 Data Sheet, Rev. 2.17
10
0
0
0
0
9
0
0
8
Description
7
0
for details.
0
6
0
5
XGSEM[7:0]
0
4
0
3
Freescale Semiconductor
2
0
0
1
0
0