mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 280

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mc9s12xd256

Manufacturer Part Number
mc9s12xd256
Description
Hcs12x Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 6 XGATE (S12XGATEV2)
SUB
Operation
RS1 – RS2
RD IMM16
Subtracts two 16 bit values and stores the result in the destination register RD.
CCR Effects
Code and CPU Cycles
280
N:
Z:
V:
C:
SUB RD, RS1, RS2
SUB RD, #IMM16
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Refer to SUBH instruction for #IMM16 operations.
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Refer to SUBH instruction for #IMM16 operations.
Z
V
Source Form
C
RD
RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8])
new
| RS1[15] & RS2[15] & RD[15]
Address
MC9S12XDP512 Data Sheet, Rev. 2.17
Mode
IMM8
IMM8
TRI
Subtract without Carry
new
| RS2[15] & RD[15]
0
1
1
0
1
1
0
0
0
1
0
0
1
0
1
new
new
Machine Code
RD
RD
RD
RS1
IMM16[15:8]
IMM16[7:0]
RS2
Freescale Semiconductor
SUB
0
0
Cycles
P
P
P

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