mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 438

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are
read-only
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
10.3.2.13 MSCAN Reserved Register
This register is reserved for factory testing of the MSCAN module and is not available in normal system
operation modes.
438
IDHIT[2:0]
IDAM[1:0]
Field
5:4
2:0
Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization
(see
mode, no message is accepted such that the foreground buffer is never reloaded.
Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see
Section 10.4.3, “Identifier Acceptance
IDHIT2
IDAM1
Section 10.4.3, “Identifier Acceptance
0
0
1
1
0
0
0
0
1
1
1
1
Table 10-16. CANIDAC Register Field Descriptions
Table 10-17. Identifier Acceptance Mode Settings
Table 10-18. Identifier Acceptance Hit Indication
IDHIT1
IDAM0
0
1
0
1
0
0
1
1
0
0
1
1
MC9S12XDP512 Data Sheet, Rev. 2.17
Filter”).
IDHIT0
Filter”).
0
1
0
1
0
1
0
1
Table 10-18
Description
Table 10-17
Identifier Acceptance Mode
Four 16-bit acceptance filters
Two 32-bit acceptance filters
Eight 8-bit acceptance filters
summarizes the different settings.
Filter closed
Identifier Acceptance Hit
summarizes the different settings. In filter closed
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
Filter 4 hit
Filter 5 hit
Filter 6 hit
Filter 7 hit
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