mc9s12xd256 Freescale Semiconductor, Inc, mc9s12xd256 Datasheet - Page 833

• Manufacturer Part Number: mc9s12xd256
• Description: Hcs12x Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

22.3.2.10 Port E Data Direction Register (DDRE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Freescale Semiconductor
DDRE[7:2]
Reset
Field
7–0
W
R
DDRE7
Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general
purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits
1 and 0, can be read regardless of whether the alternate interrupt function is enabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PORTE after changing the DDRE register.
= Unimplemented or Reserved
DDRE6
0
6
Figure 22-12. Port E Data Direction Register (DDRE)
Table 22-13. DDRE Field Descriptions
DDRE5
MC9S12XDP512 Data Sheet, Rev. 2.17
0
5
DDRE4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRE3
0
3
DDRE2
0
2
0
0
1
0
0
0
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