HD6432621 Hitachi, HD6432621 Datasheet - Page 1011

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

SSR1—Serial Status Register 1
Bit
Initial value
Read/Write
Notes: For details, see section 13.2.7, Serial Status Register (SSR).
* Can only be written with 0 for flag clearing.
:
:
:
R/(W)*
TDRE
Transmit data register empty
0 [Clearing conditions]
1
7
1
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
R/(W)*
RDRF
Receive data register full
6
0
0 [Clearing conditions]
1
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
R/(W)*
ORER
Overrun error
0 [Clearing condition]
1
5
0
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Framing error
0 [Clearing condition]
1
R/(W)*
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0
FER
4
0
Parity error
0 [Clearing condition]
1
H'FF84
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data
plus the parity bit does not match the parity setting (even or
odd) specified by the O/E bit in SMR
Transmit end
0 [Clearing conditions]
1
R/(W)*
PER
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
Multiprocessor bit
0 [Clearing condition]
1
3
0
writes data to TDR
a 1-byte serial transmit character
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
TEND
R
2
1
Multiprocessor bit transfer
0 Data with a 0 multiprocessor
1
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
MPB
R
1
0
MPBT
R/W
0
0
SCI
967