HD6432621 Hitachi, HD6432621 Datasheet - Page 559

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
14.4
The following points should be noted when using the SCI as a Smart Card interface.
Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In
Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or
256 times the transfer rate (as determined by bits BCP1 and BCP0).
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd,
186th, or 128th pulse of the basic clock. Figure 14-10 shows the receive data sampling timing
when using a clock of 372 times the transfer rate.
Internal
basic
clock
Receive
data (RxD)
Synchro-
nization
sampling
timing
Data
sampling
timing
Usage Notes
Figure 14-10 Receive Data Sampling Timing in Smart Card Mode
0
186 clocks
185
(Using Clock of 372 Times the Transfer Rate)
372 clocks
Start bit
371
0
D0
185
371 0
D1
515

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