HD6432621 Hitachi, HD6432621 Datasheet - Page 586

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning
interrupt requests caused by the receive error counter.
Bit 12: IMR4
0
1
Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error
warning interrupt requests caused by the transmit error counter.
Bit 11: IMR3
0
1
Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame
reception interrupt requests.
Bit 10: IMR2
0
1
Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception
interrupt requests.
Bit 9: IMR1
0
1
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.
542
Description
REC error warning interrupt request (OVR0) to CPU by IRR4 enabled
REC error warning interrupt request (OVR0) to CPU by IRR4 disabled
Description
TEC error warning interrupt request (OVR0) to by IRR3 CPU enabled
TEC error warning interrupt request (OVR0) to by IRR3 CPU disabled
Description
Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled
Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled
Description
Message reception interrupt request (RM1) to CPU by IRR1 enabled
Message reception interrupt request (RM1) to CPU by IRR1 disabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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