HD6432621 Hitachi, HD6432621 Datasheet - Page 994

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

TCSR0—Timer Control/Status Register 0
950
Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see
Bit
Initial value
Read/Write
section 12.2.5, Notes on register access.
* Can only be written with 0 for flag clearing.
Overflow flag
0 [Clearing conditions]
1
:
:
:
When 0 is written to OVF after reading TCSR when OVF = 1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset
R/(W)*
OVF
Timer mode select
Note: * For details of the case where TCNT overflows in watchdog timer mode,
7
0
0 Interval timer mode: Sends the CPU an interval timer interrupt request
1
(WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows *
see section 12.2.3, Reset Control/Status Register (RSTCSR).
WT/IT
R/W
Timer enable
6
0
0 TCNT is initialized to H'00 and halted
1
TCNT counts
TME
R/W
5
0
Clock select
Note: * The overflow period is the time from when TCNT
CKS2
0
1
CKS2
starts counting up until overflow occurs.
—
—
0
1
0
1
4
1
CKS2
H'FF74 (W), H'FF74 (R)
0
1
0
1
0
1
0
1
—
—
3
1
ø/2 (Initial value)
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Clock
CKS2
R/W
2
0
CKS1
25.6 s
819.2 s
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
R/W
(when ø = 20 MHz)
Overflow Period*
1
0
CKS0
R/W
WDT0
0
0