HD6432621 Hitachi, HD6432621 Datasheet - Page 14

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Section
15.3.2 Initialization
after Hardware Reset
Bit Rate and Bit Timing
Settings
Page
557 to
559
Description
Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and
bit timing setting must be made each time a CAN node begins
communication. The baud rate and bit timing settings are made in the bit
configuration register (BCR).
a.
Table 15-3 BCR Register Value Setting Ranges
b.
The following formula is used to calculate the baud rate.
Note: f
Example: With a 1 Mb/s baud rate and a 20 MHz input clock:
Name
Time segment 1
Time segment 2
Baud rate prescaler
Sample point
Re-synchronization jump width
Note
BCR can be written to at all times, but should only be modified in
configuration mode.
Settings should be made so that all CAN controllers connected to the
CAN bus have the same baud rate and bit width.
Refer to table 15.3 for the range of values that can be used as settings
(TSEG1, TSEG2, BRP, sample point, and SJW) for BCR.
Value Setting Ranges
The bit width consists of the total of the settable Time Quanta (TQ). TQ
(number of system clocks) is determined by the baud rate prescaler
(BRP).
The value of SJW is stipulated in the CAN specifications.
3
The minimum value of TSEG1 is stipulated in the CAN specifications.
TSEG1 > TSEG2
The minimum value of TSEG2 is stipulated in the CAN specifications.
TSEG2 SJW
Item
f
BRP
TSEG1
TSEG2
TQ =
CLK
Bit rate [b/s] =
1 Mb/s =
The BCR values are used for BRP, TSEG1, and TSEG2.
CLK
SJW
= f (system clock)
2
0
2
(BRP + 1)
f
CLK
(0 + 1)
2
Set Values
20 MHz
0 (B'000000)
4 (B'0100)
3 (B'011)
20 MHz
(BRP + 1)
(3 + 4 + 3)
Abbreviation
TSEG1
TSEG2
BRP
SAM
SJW
(3 + TSEG1 + TSEG2)
f
CLK
Actual Values
—
System clock
5TQ
4TQ
Min. Value
B'0000
B'000
B'000000
B'0
B'00
2
Max. Value
B'1111
B'111
B'111111
B'1
B'11