HD6432621 Hitachi, HD6432621 Datasheet - Page 721

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
20.2
20.2.1
SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
PSTOP
0
1
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
0
1
Bit
Initial value
R/W
Register Descriptions
System Clock Control Register (SCKCR)
High-speed Mode,
Medium-Speed Mode
ø output (initial value)
Fixed high
Description
Specified multiplication factor is valid after transition to software standby mode
Specified multiplication factor is valid immediately after STC bits are rewritten
:
:
:
PSTOP
R/W
7
0
6
0
Sleep Mode
ø output
Fixed high
5
0
Description
4
0
Software
Standby Mode
Fixed high
Fixed high
STCS
R/W
3
0
SCK2
R/W
2
0
SCK1
Hardware
Standby Mode
High impedance
High impedance
R/W
1
0
(Initial value)
SCK0
R/W
0
0
677

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