HD6432621 Hitachi, HD6432621 Datasheet - Page 220

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
7.8.4
Figure 7-18 shows the timing for transition to the bus-released state.
176
Address bus
HWR, LWR
BREQO *
[1]
[2]
[3]
[4]
[5]
[6]
Note: * Output only when BREQOE is set to 1.
Data bus
BREQ
BACK
RD
AS
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
BREQO signal goes high 1.5 clocks after BACK signal goes high.
ø
Transition Timing
T
0
Figure 7-18 Bus-Released State Transition Timing
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
2
state.
[2]
External bus released state
[3]
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
[5]
cycle
CPU
[6]

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