HD6432621 Hitachi, HD6432621 Datasheet - Page 446

no-image

HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
Bit 7
OVF
0
1
In interval tmer mode, to clear OVF flag in WOVI handling routine, read TCSR when OVF = 1,
then write with 0 to OVF, as stated above.
When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR
read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0 to OVF.
In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear
condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. When TCNT overflows, WDT0 generates the WDTOVF signal when in watchdog
timer mode, or a WOVI interrupt request to the CPU when in interval timer mode. WDT1
generates a reset or NMI interrupt request when in watchdog timer mode, or a WOVI interrupt
request to the CPU when in interval timer mode.
WDT0 Mode Select
WDT0
WT/IT
0
1
Note: * For details on a TCNT overflow in watchdog timer mode, see section 12.2.3, Reset
402
Control/Status Register (RSTCSR).
section 12.2.5, Notes on Register Access.
Description
[Clearing conditions]
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Description
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
Watchdog timer mode: WDT0 outputs a WDTOVF signal when the TCNT overflows.*
Cleared when 0 is written to the TME bit (Only applies to WDT1)
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
(Initial value)
(Initial value)

Related parts for HD6432621