HD6432621 Hitachi, HD6432621 Datasheet - Page 451

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS
0
1
Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
12.2.4
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control
Register (PFCR).
Bit 5—BUZZ Output Enable (BUZZE)*: Enables or disables BUZZ output from the PF1 pin.
The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.
Note: * In the H8S/2623 Series this bit is reserved, and must be written with 0.
Bit 5
BUZZE
0
1
Bit
Initial value :
R/W
Pin Function Control Register (PFCR)
Description
Power-on reset
Setting prohibited
Description
Functions as PF1 I/O pin
Functions as BUZZ output pin
:
:
R/W
—
7
0
R/W
—
6
0
BUZZE
R/W
5
0
R/W
—
4
0
AE3
R/W
1/0
3
AE2
R/W
1/0
2
AE1
R/W
1
0
(Initial value)
(Initial value)
AE0
R/W
1/0
0
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