HD6432621 Hitachi, HD6432621 Datasheet - Page 191

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

7.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Bit 5—Reserved: This bit cannot be modified and is always read as 0.
Bit 4—Reserved: Only 0 should be written to this bit.
Bit 3—Reserved: Only 1 should be written to this bit.
Bit 2—Reserved: Only 0 should be written to this bit.
Bit
Initial value
R/W
Bus Control Register L (BCRL)
Description
External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O
ports.
External bus release is enabled.
Description
BREQO output disabled. BREQO can be used as I/O port.
BREQO output enabled.
:
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
—
—
5
0
R/W
—
4
0
R/W
—
3
1
R/W
—
2
0
WDBE
R/W
1
0
(Initial value)
(Initial value)
WAITE
R/W
0
0
147