HD6432621 Hitachi, HD6432621 Datasheet - Page 278

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Port A Data Register (PADR)
Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read.
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA5 to
PA0).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Port A Register (PORTA)
Notes: *1 Determined by state of pins PA5 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA5 to PA0) must always be performed on PADR.
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as
PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.
234
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
*2 In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if
read.
:
:
:
:
Undefined Undefined
Undefined Undefined
—
—
—
—
7
7
—
—
—
—
6
6
PA5DR * PA4DR *
PA5*
R/W
—*
5
0
5
R
1
2
PA4*
R/W
—*
4
0
4
R
1
2
PA3DR
R/W
PA3
—*
3
0
3
R
1
PA2DR
R/W
PA2
—*
2
0
2
R
1
PA1DR
R/W
PA1
—*
1
0
1
R
1
PA0DR
R/W
PA0
—*
0
0
0
R
1